1. Field of the Invention
The present invention relates to a semiconductor device having semiconductor elements formed on its surface and to a method of manufacturing the semiconductor device.
2. Related Background Art
Semiconductor devices have been formed in such a manner that wiring and electrode pads are formed on a substrate such as a semiconductor substrate or a glass substrate by a semiconductor process, and a plurality of semiconductor chips are mounted on the surface of the substrate. With the miniaturization of semiconductor devices, there has been an increased need to reduce the size of the semiconductor devices and to increase the mounting density. To meet this need, connections from the back surface of a substrate to external terminals are made by providing electrical conduction between the front and back surfaces of the substrate, the back surface of the substrate is used for wiring by providing electrical conduction between the front and back surfaces, or three-dimensional mounting is performed in such a manner that a plurality of substrates are stacked and electrical connections are made between the front and back surfaces of the substrates.
Methods for providing electrical conduction between the front and back surfaces of a substrate by using a through hole formed through the substrate are known. Japanese Patent Application Laid-Open No. 9-92675 discloses a method of manufacturing a semiconductor device in which electrical conduction is provided between the front and back surfaces of a substrate by using a through hole formed through the substrate.
In the method disclosed in Japanese Patent Application Laid-Open No. 9-92675, protective layer and openings where no protective layer is formed are first formed on the front and back surfaces of a substrate on which semiconductor elements are formed in advance. Subsequently, etching with an etchant corrosive to the semiconductor substrate or etching using water jetting or laser capable of etching a small-area portion is effected at openings until the semiconductor substrate is etched through, thereby forming through holes. Subsequently, an insulating layer is formed on the front surface of the semiconductor substrate and the inside surfaces of the through holes by using thermal oxidation or chemical vapor deposition. The through holes are then closed by chemical vapor deposition or plating and electrically electroconductive layers are formed on the front and back surfaces of the substrate. Thereafter, the electroconductive layers on the front and back surfaces of the semiconductor substrate are etched back. Portions of the electroconductive layers on front and back surfaces of the semiconductor substrate other than the portions of the electroconductive layers in the through holes of the semiconductor substrate are thereby removed. Thereafter, openings are selectively formed in the protective layer and the insulating layer covering the semiconductor elements formed on the front surface of the semiconductor substrate. Subsequently, a first surface layer wiring film is formed on the substrate surface by using chemical vapor deposition, physical vapor deposition or plating. Subsequently, the first surface layer wiring film is selectively etched to form first surface layer wiring, which connects the semiconductor elements and the conductors formed in the through holes. The semiconductor elements and the first surface layer wiring are connected by the above-described process, thus providing electrical conduction from the semiconductor elements to the back surface of the semiconductor substrate via the through holes.
Japanese Patent Application Laid-Open No. 4-10649 discloses a method of manufacturing a semiconductor device in which electrical conduction is provided between the front and back surfaces of a semiconductor substrate via a through hole formed through the semiconductor substrate. Circuits and electrode pads are formed on a surface of a semiconductor substrate. Through holes are formed in the semiconductor substrate at positions at which the electrode pads are formed. Thereafter, an insulating material is stacked on the semiconductor substrate by chemical vapor deposition to fill the through holes with the insulating material. Holes smaller than the through holes are then formed through the insulating material in the through holes to expose the electrode pads at the other surface side of the semiconductor substrate. A layer of an electroconductive material such as Al is thereafter formed at the through holes by vacuum deposition and patterning is performed on the layer to form connection pads connecting to the electrode pads.
In recent years, through holes in semiconductor devices have been used in various fields, e.g., in integrated circuit substrates employed in stacked multi-chip packages (MCPs), semiconductor memories, complementary metal-oxide semiconductor (CMOS) sensors, and auto-focus (AF) sensors, micromachines, etc., in semiconductor packages in which a plurality of semiconductor chips are stacked, and for connection of ink jet heads to main units. In a case where through holes are formed in a semiconductor device for electrical conduction between front and back surfaces, if semiconductor elements or electrode pads electrically connected to semiconductor elements are formed after the formation of the through holes, there is a need to again form a wiring pattern or the like after the formation of the semiconductor elements or the electrode pads and the manufacturing process becomes complicated, resulting in an increase in manufacturing cost. To simplify the manufacturing process to reduce the manufacturing cost, a procedure is required in which semiconductor elements and electrode pads electrically connected to the semiconductor elements are formed in the vicinity of opening ends of through holes in a semiconductor substrate by using a semiconductor process, and the through holes are thereafter formed in the semiconductor substrate.
In the art disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 9-92675, however, a thermal oxidation treatment is used as a step of forming an insulating layer. In ordinary cases, a thermal oxidation treatment is performed at a high temperature of 1000° C. or higher to form a dense oxide film. It is known that in ordinary cases a failure can occur in the function of a semiconductor element when the semiconductor element is subjected to a high temperature of 600° C. or higher. Also, it is highly possible that an electrode pad formed on an electroconductive substrate by gold plating or the like will separate from the substrate if it is subjected to a high temperature of 600° C. or higher. Therefore it is difficult to use a step of forming an insulating layer by a thermal oxidation treatment in a case where semiconductor elements and electrode pads are formed on a semiconductor substrate in advance.
In Japanese Patent Application Laid-Open No. 9-92675 and Japanese Patent Application Laid-Open No. 4-10649, use of chemical vapor deposition as a step of forming an insulating layer is described. However, it is difficult to use thermal CVD among chemical vapor deposition methods in a case where semiconductor elements and electrode pads are formed on a substrate in advance, since thermal CVD ordinarily requires heating at a high temperature of 600° C. or higher, as in the case of the above-mentioned thermal oxidation treatment.
In a case where the inside surface of a through hole in a substrate is made electroconductive, for example, for the reason that the substrate is electroconductive, a leak occurs between the electroconductive semiconductor substrate and an electroconductive layer formed on the inside surface of the insulating layer, resulting in failure in the functions of the semiconductor device using the substrate. With the increase in the degree of integration or in packaging density of semiconductor devices, through holes have become reduced in bore diameter, and the aspect ratio, i.e., the ratio of the depth and the bore diameter of through holes, is increasing. Therefore there is also a need to form an insulating layer uniform in thickness and perfectly defect-free in through holes having higher aspect ratios.
However, according to the chemical vapor deposition methods described in Japanese Patent Application Laid-Open No. 9-92675 and Japanese Patent Application Laid-Open No. 4-10649, an insulating layer is ordinarily formed on the entire front and back surfaces of a semiconductor substrate as well as in a through hole. The forming speed of an insulating layer in a through hole is extremely small in comparison with that at the front and back surfaces of a semiconductor substrate, since the gas cannot easily enter the through hole and cannot circulate well. Thus, it is difficult to efficiently form an insulating layer on the inside surface of a through hole. It is also difficult to maintain the uniformity of formed layer. This phenomenon becomes noticeable in a case where an insulating film is formed on the inside surface of a through hole having a high aspect ratio or a small-diameter through hole. In particular, it is extremely difficult to form, by chemical vapor deposition, a uniform layer in a through hole of a semiconductor chip for ordinarily use when the aspect ratio is 5 or higher or when the inside diameter is 100 μm or smaller.
Also, the forming speed of an insulating layer formed in the inside surf-ace of a through hole is higher at the opening end of the through hole than at an inner portion of the through hole for the above-described reason. As a result, the film becomes thicker at the opening end of the through hole and thinner at the inner position. Thus, in some cases, there is high possibility of failure to insulate an inner portion of a through hole due to the existence of a defective portion of an insulating layer.